CY28346
PCI_STP# Assertion
time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see
Figure 14.) The PCI_F (0:2) clocks will not be affected by this
pin if their control bits in the SMBus register are set to allow
them to be free running.
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 10. CPU_STP# Deassertion Waveform
Table 7. Cypress Clock Power Management Truth Table
B0b6
B1b6
PD#
CPU_STP# Stoppable CPUT
Stoppable
CPUC
Non-Stop CPUT Non-Stop CPUC
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Running
Iref x6
Iref x2
Iref x2
Running
Hi-Z
Running
Iref x6
LOW
Running
Running
Iref x2
Iref x2
Running
Running
Hi-Z
Running
Running
LOW
LOW
LOW
Running
Hi-Z
Running
Running
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Running
Iref x6
Hi-Z
Running
Iref x6
Hi-Z
Running
Running
Hi-Z
Running
Running
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Running
Hi-Z
Running
Hi-Z
Running
Running
Hi-Z
Running
Running
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Rev 1.0,November 24, 2006
Page 10 of 19
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