CY28400-2
OE Assertion
SRC_DIV2# Deassertion
All differential outputs that were tri-stated will resume normal
operation in a glitch-free manner. The maximum latency from
the assertion to active outputs is between 2–6 DIF clock
periods. In addition, DIFT clocks will be driven high within 15
ns of OE assertion to a voltage greater than 200 mV.
The impact of deasserting the SRC_DIV2# is that all DIF
outputs will transition cleanly in a glitch-free manner from
divide by 2 mode to normal (output frequency is equal to the
input frequency) operation within 2–6 DIF clock periods.
PLL/BYPASS# Clarification
OE Deassertion
The PLL/Bypass# input is used to select between bypass
mode (no PLL) and PLL mode. In bypass mode, the input clock
is passed directly to the output stage resulting in 50-ps additive
jitter (50 ps + input jitter) on DIF outputs. In the case of PLL
mode, the input clock is pass through a PLL to reduce high
frequency jitter. The BYPASS# mode may be selected in two
ways, via writing a ‘0’ to SMBus register bit or by asserting the
PLL/BYPASS# pin low. In both methods, if the SMBus register
bit has been written to ‘0’ or PLL/BYPASS# pin is low or both,
the device will be configure for BYPASS operation.
The impact of deasserting OE is that each corresponding
output will transition from normal operation to tri-state in a
glitch-free manner. The maximum latency from the
deassertion to tri-stated outputs is between 2–6 DIF clock
periods.
SRC_DIV2# Clarification
The SRC_DIV2# input is used to configure the DIF output
mode to be equal to the SRC_IN input frequency or half the
input frequency in a glitch-free manner. The SRC_DIV2#
function may be implemented via writing a ‘0’ to SMBus
register bit.
HIGH_BW# Clarification
The HIGH_BW# input is used to set the PLL bandwidth. This
mode is intended to minimize PLL peaking when two or more
buffers are cascaded by staggering device bandwidths. The
PLL high bandwidth mode may be selected in two ways, via
writing a ‘0’ to SMBus register bit or by asserting the
HIGH_BW# pin is low or both, the device will be configured for
high-bandwidth operation.
SRC_DIV2# Assertion
The impact of asserting the SRC_DIV2# is that all DIF outputs
will transition cleanly in a glitch-free manner from normal
operation (output frequency equal to input) to half the input
frequency within 2–6 DIF clock periods.
Rev 1.0,November 21, 2006
Page 10 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
