CY28400
SRC_STOP# Clarification
The SRC_STOP# signal is an active LOW input used for clean
stopping and starting the DIF outputs (valid clock must be
present on SRCT_IN). The SRC_STOP# signal is a
de-bounced signal in that it’s state must remain unchanged
during two consecutive rising edges of DIFC to be recognized
as a valid assertion or deassertion. (The assertion and
deassertion of this signal is absolutely asynchronous.)
Table 5. SRC_STOP# Functionality
[4]
SRC_STOP#
1
0
DIFT
Normal
Iref * 6 or Float
DIFC
Normal
Low
the control register SRC_STOP# three-state bit is
programmed to ‘0’, the final state of all stopped DIFT/C signals
is DIFT clock = HIGH and DIFC = LOW. There is to be no
change to the output drive current values, DIFT will be driven
HIGH with a current value equal 6 x Iref, and DIFC will not be
driven. When the control register SRC_STOP# three-state bit
is programmed to ‘1’, the final state of all stopped DIF signals
is LOW, both DIFT clock and DIFC clock outputs will not be
driven.
SRC_STOP# Deassertion
All differential outputs that were stopped will resume normal
operation in a glitch-free manner. The maximum latency from
the deassertion to active outputs is between 2–6 DIFT/C clock
periods (two clocks are shown) with all DIFT/C outputs
resuming simultaneously. If the control register three-state bit
is programmed to ‘1’ (three-state), then all stopped DIFT
outputs will be driven high within 10 ns of SRC_STOP#
deassertion to a voltage greater than 200 mV.
SRC_STOP# Assertion
The impact of asserting the SRC_STOP# pin is all DIF outputs
that are set in the control registers to stoppable via assertion
of SRC_STOP# are stopped after their next transition. When
1mS
SRC_STOP#
PWRDWN#
DIFT(Free Running
DIFC(Free Running
DIFT (Stoppable)
DIFC (Stoppable)
Figure 4. SRC_STOP# = Driven, PWRDWN# = Driven
1mS
SRC_STOP#
PWRDWN#
DIFT(Free Running
DIFC(Free Running
DIFT (Stoppable)
DIFC (Stoppable)
Figure 5. SRC_STOP# =Driven, PWRDWN# = Three-state
Note:
4. In the case where OE is asserted HIGH, the output will always be three-stated regardless of SRC_STOP# drive mode register bit state.
Rev 1.0, November 21, 2006
Page 7 of 12
SPECTRALINEAR [ SPECTRALINEAR INC ]
