CY28405-2
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 5. VTT_PWRGD# Timing Diagram
S2
S1
VTT_PWRGD# = Low
Delay
>0.25mS
Sample
Inputs straps
VDD_A = 2.0V
Wait for <1.8ms
S0
S3
VDD_A = off
Normal
Operation
Enable Outputs
Power Off
VTT_PWRGD# = toggle
Figure 6. Clock Generator Power-up/Run State Diagram
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Condition
Min.
–0.5
–0.5
–0.5
–65
0
Max.
4.6
Unit
V
VDDA
VIN
Analog Supply Voltage
Input Voltage
4.6
V
Relative to V SS
VDD + 0.5
+150
70
VDC
°C
TS
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Non-functional
Functional
TA
°C
TJ
Functional
–
150
°C
ESDHBM
ØJC
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
V
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Flammability Rating
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
At 1/8 in.
36.9
°C/W
°C/W
ØJA
83.5
V–0
1
UL–94
MSL
Moisture Sensitivity Level
Rev 1.0,November 22, 2006
Page 10 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
