CY28405-2
Byte 1: Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
1
1
1
1
1
1
1
SRCT
SRCC
SRCT
SRCC
Reserved
Reserved
Reserved
CPUT_ITP, CPUC_ITP
CPUT1, CPUC1
CPUT0, CPUC0
Name
Description
Allow control of SRC during SW PCI_STP assertion
0 = Free Running, 1 = Stopped with SW PCI_STP
SRC Output Enable
0 = Disabled (three-state), 1 = Enabled
Reserved, set = 1
Reserved, set = 1
Reserved, set = 1
CPU_ITP Output Enable
0 = Disabled (three-state), 1 = Enabled
CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
CPUT/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
Byte 2: Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
SRCT, SRCC
SRCT, SRCC
CPUT_ITP, CPUC_ITP
CPUT1, CPUC1
CPUT0, CPUC0
Reserved
Reserved
Reserved
Description
SRCT/C Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state in power-down
SRC Stop drive mode
0 = Driven in PCI_STP, 1 = three-state in power-down
CPU(T/C)_ITP Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state in power-down
CPU(T/C)1 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state in power-down
CPU(T/C)0 Pwrdwn drive mode
0 = Driven in power-down, 1 = three-state in power-down
Reserved, set = 0
Reserved, set = 0
Reserved, set = 0
Byte 3: Control Register
Bit
7
@Pup
1
Name
SW PCI STOP
Description
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Reserved
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
Reserved
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
Rev 1.0, November 22, 2006
Page 5 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
