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CY28405OXC 参数 Datasheet PDF下载

CY28405OXC图片预览
型号: CY28405OXC
PDF下载: 下载PDF文件 查看货源
内容描述: CK409兼容的时钟合成器 [CK409-Compliant Clock Synthesizer]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 18 页 / 198 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28405
Pin Description
Pin No.
1, 2
REF(0:1)
Name
Type
O, SE
I
I
Description
Reference Clock.
3.3V 14.318-MHz clock output.
3.3V LVTTL latched input for CPU frequency selection.
Crystal Connection or External Reference Frequency Input.
This pin
has dual functions. It can be used as an external 14.318-MHz crystal
connection or as an external reference frequency input.
Crystal Connection.
Connection for an external 14.318-MHz crystal
output.
CPU Clock Output.
Differential CPU clock outputs.
CPU Clock Output.
Differential CPU clock outputs.
Do Not Connect.
O, SE
I/O, SE
PD
I/O, SE
PU
66-MHz Clock Output.
3.3V 66-MHz clock from internal VCO.
48- or 66-MHz Clock Output.
3.3V selectable through external SELVCH
strapping resistor and SMBus to be 66-MHz or 48-MHz. Default is 66-MHz.
0 = 66 MHz, 1 = 48 MHz
66-MHz Clock Output.
3.3V 66-MHz clock from internal VCO. Reset or
Power-down Mode Select. Selects between RESET# output or PWRDWN#
input for the PWRDWN#/RESET# pin. Default is RESET#. 0 = PD#, 1 =
RESET
Free Running PCI Output.
33-MHz clocks divided down from 3V66.
PCI Clock Output.
33-MHz clocks divided down from 3V66.
Fixed 48-MHz clock output.
Fixed 48-MHz clock output.
Current Reference.
A precision resistor is attached to this pin which is
connected to the internal current reference.
3.3V LVTTL input for Power-down# active LOW.
Watchdog Timeout
Reset Output
3.3V LVTTL input is a level sensitive strobe used to latch the FS[A:E]
input (active LOW).
SMBus compatible SDATA.
SMBus compatible SCLOCK.
3.3V Power supply for PLL.
Ground for PLL.
3.3V Power supply for outputs.
1, 2, 7, 8, 9 FS_A, FS_B, FS_C,
FS_D, FS_E
4
XIN
5
39, 42, 45
38, 41, 44
36, 35
30, 29
25
XOUT
CPUT(0:1,ITP)
CPUC(0:1,ITP)
DNC
3V66(0:1)
3V66_3/VCH/SELVCH
O, SE
O, DIF
O, DIF
26
3V66_2/MODE
7, 8, 9
PCIF(0:2)
O, SE
O, SE
O, SE
O, SE
I
I/O, PU
I
I/O
I
PWR
GND
PWR
12, 13, 14, PCI(0:5)
15, 18, 19
22
21
46
20
33
32
31
48
47
USB_48
DOT_48
IREF
RESET#/PD#
VTT_PWRGD#
SDATA
SCLK
VDDA
VSSA
3, 10, 16, VDD(REF,PCI,48,3V66,C
24, 27, 34, PU,ITP)
40
6, 11, 17, VSS(REF,PCI,48,3V66,
23, 28, 37, CPU,ITP)
43
GND
Ground for outputs.
Rev 1.0, November 20, 2006
Page 2 of 18