CY28408
Pin Description
Pin
2
3
Name
XIN
XOUT
PWR
VDD
VDD
VDD
VDDP
VDD
VDD
I/O
I
O
O
O
I/O
PD
O
Description
Oscillator buffer input.
Connect to a crystal or to an external clock.
Oscillator buffer output.
Connect to a crystal. Do not connect when an
external clock is applied at XIN.
Differential host output clock pairs.
See
Table 1
for frequencies and
functionality.
PCI clock outputs.
Synchronous to the 3V66 clock. See
Table 1.
Early or normal PCI clock outputs.
There is an internal 250k
pull-down resistor. See
Table 8.
33-MHz PCI clocks,
which are 2 copies of 3V66 clocks, may be free running
(not stopped when PCI_STP# is asserted LOW) or may be stoppable
depending on the programming of SMBus register Byte3, Bits (3:5).
Buffered output copy of the device’s XIN clock.
Current reference programming input for CPU buffers.
A resistor is
connected between this pin and VSSIREF.
Qualifying input that latches S(0:2) and MULT0.
When this input is at
a logic low, the S(0:2) and MULT0 are latched
Fixed 48-MHz USB clock outputs.
Fixed 48-MHZ DOT clock outputs.
3.3V 66-MHz fixed frequency clock.
3.3V clock selectable with SMBus byte0, Bit5, when Byte5, Bit5.
When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When
byte0, Bit5 is a logic 0, then this is a 66-MHz output clock (default).
3.3V 66-MHz fixed frequency clock.
This pin is a power-down mode pin.
A logic LOW level causes the
device to enter a power-down state. All internal logic is turned off except
for the SMBus logic. All output buffers are stopped.
Programming input selection for CPU clock current multiplier.
0 = 4 * IREF, 1 = 6 * =IREF
Frequency select inputs.
See
Table 1
Serial data input.
Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open
drain output when acknowledging or transmitting data.
Serial clock input.
Conforms to the SMBus specification.
52, 51, 49, 48,
CPUT(0:2),
45, 44
CPUC(0:2)
10, 12, 16, 17, 18 PCI(0,2)/(3:5)
11,13
EPCI/PCI(1,3)
5, 6, 7
PCIF (0:2)
56
42
28
39
38
33
35
REF
IREF
VTT_PWRGD#
48M_USB
48M_DOT
3V66_0
3V66_1/VCH
VDD
VDD
VDD
VDD48
VDD48
VDD
VDD
O
I
I
O
O
O
O
21, 22, 23, 24
25
3V66(2:5)
PD#
VDD
VDD
O
I
PU
I
PU
I
I/O
PU
I
PU
I
T
I
PU
43
55, 54
29
MULT0
S(0,1)
SDATA
VDD
VDD
VDD
30
40
34
SCLK
S2
PCI_STP#
VDD
VDD
VDD
53
CPU_STP#
VDD
1, 8, 14, 19, 32,
37, 46, 50
4, 9, 15, 20, 27,
31, 36, 47
41
VDD
VSS
VSSIREF
–
–
–
Frequency select input.
See
Table 1.
This is a tri-level input that is
driven HIGH, LOW, or driven to a intermediate level.
PCI clock disable input.
When asserted LOW, PCI (0:6) clocks are
synchronously disabled in a LOW state. This pin does not effect PCIF
(0:2) clock outputs if they are programmed to be PCIF clocks via the
device’s SMBus interface.
I
CPU clock disable input.
When asserted LOW, CPUT (0:2) clocks are
PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are
synchronously disabled in a LOW state.
PWR 3.3V power supply.
PWR Common ground.
PWR
Current reference programming input for CPU buffers.
A resistor is
connected between this pin and IREF. This pin should also be returned
to device VSS.
PWR
Analog power input.
Used for PLL and internal analog circuits. It is also
specifically used to detect and determine when power is at an acceptable
level to enable the device to operate.
26
VDDA
–
Rev 1.0, November 20, 2006
Page 2 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
