CY28419
Byte 6: Control Register 6
Bit
7
@Pup
0
REF
PCIF
PCI
3V66
USB_48
DOT_48
CPUT/C
SRCT/C
CPUC0, CPUT0
CPUC1, CPUT1
CPUC2, CPUT2
CPUC3, CPUT3
SRCT, SRCC
Name
Test Clock Mode
0= Disabled, 1 = Enabled
Description
6
5
0
0
Reserved, Set = 0
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
3
2
0
0
0
SRC Frequency Select
0 = 100 MHz, 1 = 200 MHz
Reserved, Set = 0
Spread Spectrum Mode
0 = Spread Off, 1 = Spread On
PCIF
PCI
3V66
SRC(T/C)
CPUT/ C
REF_1
REF_0
1
0
1
1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 7: Vendor ID
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Crystal Recommendations
The CY28419 requires a
Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28419 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Table 6. Crystal Recommendations
Frequency
(Fund)
14.31818 MHz
Cut
AT
Loading Load Cap
Parallel
20 pF
Drive
(max.)
0.1 mW
Shunt Cap
(max.)
5 pF
Motional
(max.)
0.016 pF
Tolerance
(max.)
50 ppm
Stability
(max.)
50 ppm
Aging
(max.)
5 ppm
Rev 1.0, November 22, 2006
Page 7 of 15