CY28435
Byte 11: Control Register 11
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
CPU_DAF_N7
CPU_DAF_N6
CPU_DAF_N5
CPU_DAF_N4
CPU_DAF_N3
CPU_DAF_N2
CPU_DAF_N1
CPU_DAF_N0
Description
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[E:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used.
Byte 12: Control Register 12
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
CPU_DAF_N8
CPU_DAF_M6
CPU_DAF_M5
CPU_DAF_M4
CPU_DAF_M3
CPU_DAF_M2
CPU_DAF_M1
CPU_DAF_M0
Description
If Prog_CPU_EN is set, the values programmed is in CPU_FSEL_N[8:0]
and CPU_FSEL_M[6:0] will be used to determine the CPU output
frequency.
The setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the Latched FS[E:A] register will be used. When it is set, the
frequency ratio stated in the FSEL[3:0] register will be used.
Byte 13: Control Register 13
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
SRC_N7
SRC_N6
SRC_N5
SRC_N4
SRC_N3
SRC_N2
SRC_N1
SRC_N0
SRC Dial-A-Frequency Bit N7
SRC Dial-A-Frequency Bit N6
SRC Dial-A-Frequency Bit N5
SRC Dial-A-Frequency Bit N4
SRC Dial-A-Frequency Bit N3
SRC Dial-A-Frequency Bit N2
SRC Dial-A-Frequency Bit N1
SRC Dial-A-Frequency Bit N0
Description
Byte 14: Control Register 14
Bit
7
6
@Pup
0
0
Name
SRC_N8
SW_RESET
SRC Dial-A-Frequency Bit N8
Software Reset.
When set the device will assert a reset signal on SRESET# upon
completion of the block/word/byte write that set it. After asserting and
deasserting the SRESET# this bit will self clear (set to 0).
The SRESET# pin must be enabled by latching SRESET#_EN on
VTT_PRWGD# to utilize this feature.
FS_Override
0 = Select operating frequency by FS(E:A) input pins
1 = Select operating frequency by FSEL_(4:0) settings
Smooth switch select
0: select CPU_PLL
1: select SRC_PLL.
RESERVED, Set = 0
RESERVED, Set = 0
Description
5
0
FS_[E:A]
4
0
SMSW_SEL
3
2
0
0
RESERVED
RESERVED
Rev 1.0, November 20, 2006
Page 9 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
