CY28435
Control Registers
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4_SATA
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
RESERVED
Description
SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4_SATA Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
RESERVED, Set = 1
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
0
1
1
0
Name
PCIF0
DOT_96T/C
USB48_0
REF0
RESERVED
CPU[T/C]1
CPU[T/C]0
CPU
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB48_0 MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
RESERVED, Set = 0
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Description
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
@Pup
1
1
1
1
1
1
1
Name
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
PCIF2
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
Description
Rev 1.0, November 20, 2006
Page 5 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
