CY28442-2
Pin Definitions
(continued)
Pin No.
48
49
50
51
52
53
VDDA2
XOUT
XIN
VSSA2
REF1
FS_C_TEST_SEL/
REF0
Name
Type
PWR
I
GND
O
I/O
3.3V power supply for PLL2
14.318 MHz crystal input.
Ground for PLL2.
Fixed 14.318 MHz clock output.
3.3V-tolerant input for CPU frequency selection/fixed 14.318 clock output.
Selects test mode if pulled to greater than 1.8V when VTT_PWRGD# is asserted
LOW.
Refer to DC Electrical Specifications table for
V
IL_FS
,V
IH_FS
specifications.
3.3V LVTTL input for CPU_STP# active LOW.
3.3V LVTTL input for PCI_STP# active LOW.
O, SE
14.318 MHz crystal output.
Description
54
55
56
CPU_STP#
PCI_STP#
I, PU
I, PU
PCI2/SEL_CLKREQ I/O, PD
3.3V-tolerant input for CLKREQ pin selection/fixed 33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1= pins 32,33 function as clk request pins, 0= pins 32,33 function as SRC outputs.
Table 1. Frequency Select Table FS_A, FS_B, and FS_C
FS_C
1
0
0
0
FS_B
0
0
1
1
FS_A
1
1
1
0
CPU
100 MHz
133 MHz
166 MHz
200 MHz
SRC
100 MHz
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
USB
48 MHz
48 MHz
48 MHz
48 MHz
Frequency Select Pins (FS_A, FS_B, and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled LOW by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B, and FS_C input values. For all logic
levels of FS_A, FS_B, and FS_C, VTT_PWRGD# employs a
one-shot functionality in that once a valid LOW on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B, and FS_C transitions will be ignored, except in
test mode.
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
Table 2. Command Code Definition
Bit
7
(6:0)
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Rev 1.0, November 21, 2006
Page 3 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
