欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY2SSTV16857ZXCT 参数 Datasheet PDF下载

CY2SSTV16857ZXCT图片预览
型号: CY2SSTV16857ZXCT
PDF下载: 下载PDF文件 查看货源
内容描述: 14位Regstered缓冲PC2700- / PC3200兼容 [14-Bit Regstered Buffer PC2700-/PC3200-Compliant]
分类和应用: PC
文件页数/大小: 7 页 / 91 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第1页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第2页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第3页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第5页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第6页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第7页  
CY2SSTV16857
Table 1. DC Electrical Specifications
(V
DD
= Temperature = 0°C to +85 °C) (continued)
Parameter
V
OH
Description
Output Voltage, High
Condition
V
DD
/V
DDQ
= 2.3V to 2.7V, I
OH
=
–100 A, V
DD
=2.3 to 2.7V
V
DD
/V
DDQ
= 2.3V, I
OH
= –16 mA
I
IL
Input Current
Data Inputs
V
I
= 1.7V or 0.8V, V
REF
= 1.15V or
1.35V, V
DD
= 2.7V
V
I
= 2.7V or 0,V
REF
= 1.15V or
1.35V, V
DD
= 2.7V
V
I
= 1.7V or 0.8V, V
REF
= 1.15V or
1.35V, V
DD
= 3.6V
V
I
= 2.7V or 0
CLK, CLK
V
I
= 1.7V or 0.8V, V
REF
= 1.15V or
1.35V
V
I
= 2.7V or 0, V
REF
= 1.15V or
1.35V, V
dd
= 2.7V
RESET
VREF
I
IH
I
DD
Input Current, High
Dynamic Supply Current
V
I
= V
DD
or V
SS
, V
DD
= 2.7V
V
I
= 1.5V or 1.35V, V
DD
= 2.7
Data inputs only
V
I
= 1.7V or 0.8V, I
O
= 0, V
DD
=
2.7V
V
I
= 2.7V or 0, I
O
= 0, V
DD
= 2.7V
C
in
Input pin capacitance
RESET
Clock and Data Inputs
L
pin
Pin Inductance
All
V
I
= 1.7V or 0.8V, I
O
= 0, V
DD
=
2.7V
2.5
2.1
3
2.7
3.5
4.5
pF
pF
nH
90
90
±5
±5
±5
±5
±1
±1
±5
±5
A
A
A
A
A
A
A
A
mA.
mA
mA
Min.
V
DD
0.2
1.95
Typ.
Max.
Unit
V
Table 2. AC Input Electrical Specifications
(V
DD
= 2.5 VDC ± 5%, Temperature = 0°C to +85°C)
V
DD
= 2.5V ± 0.2V
Parameter
F
IN
P
W
T
ACT
T
INACT
T
SET
Description
Input Clock Frequency
Pulse Duration
Differential Inputs Active Time
CLK, CLK
CLK, CLK HIGH or LOW
Data inputs must be LOW after RESET HIGH
3.3
22
22
0.75
0.9
0.75
0.9
360
Condition
Min.
Max.
200
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
mV
Differential Inputs Inactive Time Data and clock inputs must be held at valid levels (not
floating) after RESET LOW
Set-up Time
Fast slew rate, (see notes 5 and 7), Data before CLK,
CLK
Slow slew rate, (see notes 6 and 7), Data before CLK,
CLK
T
HOLD
I
Vpp
Hold Time
Input Voltage, Pk–Pk
Fast slew rate, (see notes 5 and 7), Data after CLK, CLK
Slow slew rate (see notes 6 and 7), Data after CLK, CLK
Notes:
5. For data signal input slew rate > 1 V/ns.
6. For data signal input slew rate > 0.5 V/ns and < 1 V/ns.
7. CLK, CLK signals input slew rates are > 1 V/ns.
Rev 1.0, November 21, 2006
Page 4 of 7