CY2SSTV855
Absolute Maximum Conditions
[3]
Input Voltage Relative to V
SS
:............................... V
SS
– 0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................ –65 C to + 150 C
Operating Temperature:................................ –40 C to +85 C
Maximum Power Supply: ................................................ 3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
in
or V
out
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Electrical Specifications
(
AV
DD
= V
DDQ
= 2.5V ± 5%, T
A
= –40°C to +85°C)
[4]
Parameter
V
ID
V
IX
I
IN
I
OL
I
OH
V
OL
V
OH
V
OUT
V
OC
I
OZ
I
DDQ
I
DD
Cin
Description
Differential Input Voltage
[5]
Conditions
CLKINT, FBINT
Min.
0.36
(V
DDQ
/2) –
0.2
–10
26
–18
1.7
1.1
(V
DDQ
/2) –
0.2
Typ.
V
DDQ
/2
–
35
–32
–
–
–
V
DDQ
/2
Max.
V
DDQ
+ 0.6
(V
DDQ
/2) +
0.2
10
–
–
0.6
–
V
DDQ
– 0.4
(V
DDQ
/2) +
0.2
10
300
12
–
Unit
V
V
µA
mA
mA
V
V
V
V
µA
mA
mA
pF
Differential Input Crossing Voltage
[6]
CLKTIN, FBINT
Input Current
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
[7]
Output Crossing Voltage
[8]
High-Impedance Output Current
Dynamic Supply Current
[9]
PLL Supply Current
Input Pin Capacitance
V
O
= GND or V
O
= V
DDQ
V
DDQ
= 170 MHz
AV
DD
only
V
IN
= 0V or V
IN
= V
DDQ
, CLKINT,
FBINT
V
DDQ
= 2.375V, V
OUT
= 1.2V
V
DDQ
= 2.375V, V
OUT
= 1V
V
DDQ
= 2.375V, I
OL
= 12 mA
V
DDQ
= 2.375V, I
OH
= –12 mA
–10
–
–
–
235
9
4
AC Electrical Specifications
(
AV
DD
= V
DDQ
= 2.5V±5%, T
A
= –40°C to +85°C)
[10, 11]
Parameter
f
CLK
t
DC
t
LOCK
t
SL(O)
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
CCJ
t
JITT(H-PER)
Description
Operating Clock Frequency
Input Clock Duty Cycle
[12]
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time (all outputs)
[13]
Output Disable Time (all outputs)
[13]
Cycle to Cycle Jitter
Half-period jitter
Conditions
AV
DD
= 2.5V
0.2V
Min.
60
40
Typ.
Max.
170
60
100
2
Unit
MHz
%
µs
V/ns
ns
ns
20% to 80% of VOD
1
30
10
f > 66 MHz
f > 66 MHz
–100
–100
100
100
ps
ps
Notes:
3.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the comple-
mentary input level.
6. Differential cross-point input voltage is expected to track V
DDQ
and is the voltage at which the differential signals must be crossing.
7. For load conditions see
Figure 6.
8. The value of V
OC
is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120 resistor. See
Figure 6.
9. All outputs switching loaded with 16 pF in 60 environment. See
Figure 6.
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
11. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a
downspread of –0.5%
12. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
WH
/t
C
,
where the cycle time (t
C
) decreases as the frequency goes up.
13. Refers to transition of non-inverting output.
14. All differential input and output terminals are terminated with 120 /16 pF as shown in
Figure 6.
Rev 1.0, November 21, 2006
Page 5 of 6
SPECTRALINEAR [ SPECTRALINEAR INC ]
