CY2SSTV857LFI-32T[15] 参数 Datasheet PDF下载

CY2SSTV857-32

Absolute Maximum Conditions

[2]

Input Voltage Relative to V

SS

:............................... V

SS

– 0.3V

Input Voltage Relative to V

DDQ

or AV

DD

: ........... V

DDQ

+ 0.3V

Storage Temperature: ................................ –65°C to + 150°C

Operating Temperature:................................ –40°C to +85°C

Maximum Power Supply: ................................................ 3.5V

This device contains circuitry to protect the inputs against

damage due to high static voltages or electric field; however,

precautions should be taken to avoid application of any

voltage higher than the maximum rated voltages to this circuit.

For proper operation, V

in

and V

out

should be constrained to the

range:

V

SS

< (V

in

or V

out

) < V

DDQ

.

Unused inputs must always be tied to an appropriate logic

voltage level (either V

SS

or V

DDQ

).

Min.

2.375

–

0.7 × V

DDQ

[4]

DC Electrical Specifications

[3]

Parameter

V

DDQ

V

IL

V

IH

V

ID

V

IX

I

IN

I

OL

I

OH

V

OL

V

OH

V

OUT

V

OC

I

OZ

I

DDQ

I

DD

I

DDS

Cin

Description

Supply Voltage

Input Low Voltage

Input High Voltage

Differential Input Voltage

CLK, FBIN

CLK, FBIN

Differential Input Crossing

Voltage

[5]

Output Low Current

Output High Current

Output Low Voltage

Output High Voltage

Output Voltage Swing

[6]

Output Crossing Voltage

[7]

Operating

PD#

Condition

Typ.

–

–

–

–

Max.

2.625

0.3 × V

DDQ

–

V

DDQ

+ 0.6

(V

DDQ

/2) + 0.2

10

–

–

0.6

–

V

DDQ

– 0.4

(V

DDQ

/2) + 0.2

10

300

12

100

3.5

Unit

V

V

V

V

V

µA

mA

mA

V

V

V

V

µA

mA

mA

µA

pF

0.36

(V

DDQ

/2) – 0.2 V

DDQ

/2

–10

26

28

–

1.7

1.1

–10

–

–

–

2

–

35

–32

–

–

–

–

235

9

–

–

Input Current [CLK, FBIN, PD#] V

IN

= 0V or V

IN

= V

DDQ

V

DDQ

= 2.375V, V

OUT

= 1.2V

V

DDQ

= 2.375V, V

OUT

= 1V

V

DDQ

= 2.375V, I

OL

= 12 mA

V

DDQ

= 2.375V, I

OH

= –12 mA

(V

DDQ

/2) – 0.2 V

DDQ

/2

All V

DDQ

, F

O

= 200 MHz

V

DDA

only

PD# = 0 and CLK/CLK# = 0 MHz

High-Impedance Output Current V

O

= GND or V

O

= V

DDQ

Dynamic Supply

Current

[8]

PLL Supply Current

Standby Supply Current

Input Pin Capacitance

AC Electrical Specifications

[9, 10]

Parameter

f

CLK

t

DC

t

LOCK

D

TYC

tsl(o)

t

PZL

, t

PZH

t

PLZ

, t

PHZ

Description

Operating Clock Frequency

Input Clock Duty Cycle

Maximum PLL Lock Time

Duty Cycle

[11]

Condition

AV

DD

, V

DDQ

= 2.6V

0.1V

Min.

60

40

–

Typ.

–

–

–

50

–

3

3

Max.

230

60

100

51

52

2

25

8

Unit

MHz

%

s

%

%

V/ns

ns

ns

60 MHz to 100 MHz

101 MHz to 170 MHz

20%–80% of VOD

49

48

1

–

–

Output Clocks Slew Rate

Output Enable Time

[12]

(all outputs)

Output Disable Time

[12]

(all outputs)

Notes:

2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

3. Unused inputs must be held HIGH or LOW to prevent them from floating.

4. Differential input signal voltage specifies the differential voltage VTR–VCPI required for switching, where VTR is the true input level and VCP is the complementary

input level. See

Figure 6.

5. Differential cross-point input voltage is expected to track V

DDQ

and is the voltage at which the differential signal must be crossing.

6. For load conditions see

Figure 6.

7. The value of VOC is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120 resistor. See

Figure 6.

8. All outputs switching load with 14 pF in 60 environment. See

Figure 6.

9. Parameters are guaranteed by design and characterization. Not 100% tested in production.

10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 50 kHz with a down

spread or –0.5%.

11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t

WHC

/t

C

,

where the cycle time(tC) decreases as the frequency goes up.

12. Refers to transition of non-inverting output.

Rev 1.0, November 21, 2006

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