W320-03
Function Table
S2
1
1
1
1
0
0
0
0
Mid
Mid
Mid
Mid
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
S0
[1]
CPU
(MHz)
66 MHz
100 MHz
200 MHz
133 MHz
66 MHz
100 MHz
200 MHz
133 MHz
Hi-Z
TCLK/2
Reserved
Reserved
3V66[0:1] 66BUFF[0:2]/3 66IN/3V66_5
(MHz)
V66[2:4] (MHz)
(MHz)
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
TCLK/4
Reserved
Reserved
66 IN
66 IN
66 IN
66 IN
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
TCLK/4
Reserved
Reserved
66 MHz Input
66 MHz Input
66 MHz Input
66 MHz Input
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
TCLK/4
Reserved
Reserved
PCI_F/PCI
(MHz)
66 IN/2
66 IN/2
66 IN/2
66 IN/2
33 MHz
33 MHz
33 MHz
33 MHz
Hi-Z
TCLK/8
Reserved
Reserved
REF0(MHz)
USB/DOT
(MHz)
Notes
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
1, 5
6, 7, 8
–
–
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
14.318 MHz 48 MHz
Hi-Z
TCLK
Reserved
Reserved
Hi-Z
TCLK/2
Reserved
Reserved
Swing Select Functions
Mult0
0
1
Board Target
Trace/Term Z
60
50
Reference R, IREF
=
V
DD
/(3*Rr)
Rr = 221 1%,
IREF = 5.00 mA
Rr = 475 1%,
IREF = 2.32 mA
Output
Current
I
OH
= 4*IREF
I
OH
= 6*IREF
V
OH
@ Z
1.0V @ 50
0.7V @ 50
Clock Driver Impedances
Impedance
Minimum
Buffer Name
CPU, CPU#
REF
PCI, 3V66, 66BUFF
USB
DOT
3.135–3.465
3.135–3.465
3.135–3.465
3.135–3.465
V
DD
Range
Buffer Type
Type X1
Type 3
Type 5
Type 3A
Type 3B
20
12
12
12
50
40
30
30
30
60
55
55
55
Typical
Maximum
Clock Enable Configuration
PWR_DWN# CPU_STOP# PCI_STOP#
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
CPU
IREF*2
IREF*2
IREF*2
ON
ON
CPU#
FLOAT
FLOAT
FLOAT
ON
ON
3V66
LOW
ON
ON
ON
ON
66BUFF
LOW
ON
ON
ON
ON
PCI_F
LOW
ON
ON
ON
ON
PCI
LOW
OFF
ON
OFF
ON
USB/DOT
LOW
ON
ON
ON
ON
VCOS/
OSC
OFF
ON
ON
ON
ON
Notes:
1. TCLK is a test clock driven in on the XTALIN input in test mode.
2. “Normal” mode of operation.
3. Range of reference frequency allowed is min. = 14.316 nominal = 14.31818 MHz, max = 14.32 MHz.
4. Frequency accuracy of 48 MHz must be +167PPM to match USB default.
5. Mid is defined a Voltage level between 1.0V and 1.8V for 3 level input functionality. Low is below 0.8V. High is above 2.0V.
6. TCLK is a test clock over driven on the XTAL_IN input during test mode.
7. Required for DC output impedance verification.
8. These modes are to use the SAME internal dividers as the CPU = 200-MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.
Rev 1.0, November 25, 2006
Page 3 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
