SC660E
2-Wire SMBus Control Interface
The 2-wire control interface implements a write only slave
interface. The device cannot be read back. Sub-addressing is
not supported, thus all preceding bytes must be sent in order
to change one of the control bytes. The 2-wire control
interface allows each clock output to be individually enabled
or disabled.
During normal data transfer, the SDATA signal only changes
when the SDCLK signal is low, and is stable when SDCLK is
high. There are two exceptions to this. A high to low transition
on SDATA while SDCLK is high is used to indicate the start of
a data transfer cycle. A low to high transition on SDATA while
SDCLK is high indicates the end of a data transfer cycle. Data
is always sent as complete 8-bit bytes, after which an
acknowledge is generated. The first byte of a transfer cycle is
a 7-bit address with a Read/Write bit as the LSB. Data is
transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to
address
D2
by generating the acknowledge (low) signal on the
SDATA wire following reception of each byte. The device will
not respond to any other control interface conditions. Previ-
ously set control registers are retained.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
bytes must be sent:
1. “Command
Code
“ byte, and
2. “Byte
Count”
byte.
Although the data (bits) in the command is considered “don’t
care”; it must be sent and will be acknowledged.
After the Command Code and the Byte Count have been
acknowledged, the sequence (Byte 0, Byte 1, and Byte 2)
described below will be valid and acknowledged.
Byte 0:
Function Select Register (1
= enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
-
-
-
-
7
6
3
2
reserved
reserved
reserved
reserved
SDRAM3 (Active = 1, Forced low = 0)
SDRAM2 (Active = 1, Forced low = 0)
SDRAM1 (Active = 1, Forced low = 0)
SDRAM0 (Active = 1, Forced low = 0)
Description
Byte 1:
Clock Register
(1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
27
26
23
22
-
-
-
-
Description
SDRAM9 (Active = 1, Forced low = 0)
SDRAM8 (Active = 1, Forced low = 0)
SDRAM7 (Active = 1, Forced low = 0)
SDRAM6 (Active = 1, Forced low = 0)
reserved
reserved
reserved
reserved
Byte 2: Clock Register
( 1 = enable, 0 = Stopped )
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
0
0
0
0
1
1
Pin#
18
11
-
-
-
-
-
-
Description
SDRAM5 (Active = 1, Forced low = 0)
SDRAM4 (Active = 1, Forced low = 0)
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Rev 1.0, December 06, 2006
Page 3 of 5
SPECTRALINEAR [ SPECTRALINEAR INC ]
