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SL15100ZI-XXX 参数 Datasheet PDF下载

SL15100ZI-XXX图片预览
型号: SL15100ZI-XXX
PDF下载: 下载PDF文件 查看货源
内容描述: Prigrammable扩频时钟发生器( SSCG ) [Prigrammable Spread Spectrum Clock Generator (SSCG)]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 16 页 / 192 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL15100
AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C
Parameter
Input Frequency Range
Input Frequency Range
Symbol
FIN1
FIN2
Condition
Crystal or Ceramic Resonator
External Clock
SSCLK
REFCLK, crystal or resonator input
REFCLK, clock input
SSCLK
REFCLK
Clock Input, Pin 3
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
Programmable, VDD=3.3
CL=15pF, 20 to 80% of VDD
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=Off
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=Off
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=Off
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=On
CLKIN=SSCLK=66MHz, 2%Spread
REFCLK=On
CLKIN=SSCLK=33MHz, 2%Spread
REFCLK=On
CLKIN=SSCLK=166MHz, 2%Spread
REFCLK=On
Min
8
8
3
0.25
0.25
45
45
40
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
50
50
50
4.00
2.00
1.40
1.10
0.85
0.70
0.55
90
100
120
100
105
180
80
Max
48
166
200
48
166
55
55
60
4.80
2.40
1.70
1.35
1.00
0.85
0.67
120
130
160
130
140
240
100
Unit
MHz
MHz
MHz
MHz
MHz
%
%
%
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
Output Frequency Range
FOUT1
Output Frequency Range
FOUT2
Output Frequency Range
FOUT3
Output Duty Cycle
Output Duty Cycle
Input Duty Cycle
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
Cycle-to-Cycle Jitter
(SSCLK – Pin 7)
Cycle-to-Cycle Jitter
(SSCLK – Pin 6)
DC1
DC2
DCIN
tr/f1
tr/f2
tr/f3
tr/f4
tr/f5
tr/f6
tr/f7
CCJ1
CCJ2
CCJ3
CCJ4
CCJ5
CCJ6
CCJ7
Rev 1.8, August 10, 2007
Page 5 of 16