W196
Serial Data Interface
The W196 features a two-pin, serial data interface that can be
used to configure internal register settings that control
particular device functions. Upon power-up, the W196
initializes with default register settings. Therefore, the use of
this serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
Table 2. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
Description
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Provides CPU/PCI frequency selections beyond
the selections that are provided by the FS0:1 pins.
Frequency is changed in a smooth and controlled
fashion.
All clock outputs toggle in relation to X1 input,
internal PLL is bypassed. Refer to
Table 4.
Reserved function for future device revision or
production device testing.
Common Application
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to
unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change under
normal system operation.
Production PCB testing.
No user application. Register bit must be written
as 0.
outputs of the chipset. Clock device register changes are
normally made upon system initialization, if required. The
interface can also be used during system operation for power
management functions.
Table 2
summarizes the control
functions of the serial data interface.
Operation
Data is written to the W196 in ten bytes of eight bits each.
Bytes are written in the order shown in
Table 3.
CPU Clock Frequency
Selection
Output Three-state
Test Mode
(Reserved)
Puts all clock outputs into a high-impedance state. Production PCB testing.
Table 3. Byte Writing Sequence
Byte
Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
Byte Description
Commands the W196 to accept the bits in Data Bytes 3–6 for internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W196 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W196, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Unused by the W196, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
Refer to Cypress SDRAM drivers.
2
Command
Code
Don’t Care
3
Byte Count
Don’t Care
4
5
6
7
8
9
10
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Don’t Care
Refer to
Table 4
The data bits in these bytes set internal W196 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to
Table 4,
Data Byte Serial Configuration Map.
Rev 1.0, November 28, 2006
Page 5 of 11
SPECTRALINEAR [ SPECTRALINEAR INC ]
