2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
Data# Polling (DQ
7
)
When the SST39LF200A/400A/800A and SST39VF200A/
400A/800A are in the internal Program operation, any
attempt to read DQ
7
will produce the complement of the
true data. Once the Program operation is completed, DQ
7
will produce true data. The device is then ready for the next
operation. During internal Erase operation, any attempt to
read DQ
7
will produce a ‘0’. Once the internal Erase opera-
tion is completed, DQ
7
will produce a ‘1’. The Data# Polling
is valid after the rising edge of fourth WE# (or CE#) pulse
for Program operation. For Sector-, Block- or Chip-Erase,
the Data# Polling is valid after the rising edge of sixth WE#
(or CE#) pulse. See Figure 6 for Data# Polling timing dia-
gram and Figure 17 for a flowchart.
Software Data Protection (SDP)
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide the JEDEC approved Software Data Protec-
tion scheme for all data alteration operations, i.e., Program
and Erase. Any Program operation requires the inclusion of
the three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte sequence. This group of
devices are shipped with the Software Data Protection per-
manently enabled. See Table 4 for the specific software
command codes. During SDP command sequence, invalid
commands will abort the device to Read mode within TRC.
The contents of DQ
15
-DQ
8
can be V
IL
or V
IH
, but no other
value, during any SDP command sequence.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diagram and Figure 17 for a flowchart.
Common Flash Memory Interface (CFI)
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A also contain the CFI information to describe the char-
acteristics of the device. In order to enter the CFI Query
mode, the system must write three-byte sequence, same
as Software ID Entry command with 98H (CFI Query com-
mand) to address 5555H in the last byte sequence. Once
the device enters the CFI Query mode, the system can
read CFI data at the addresses given in Tables 5 through 9.
The system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
Data Protection
The SST39LF200A/400A/800A and SST39VF200A/400A/
800A provide both hardware and software features to pro-
tect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
©2001 Silicon Storage Technology, Inc.
S71117-04-000 6/01
360
3
SST [ SILICON STORAGE TECHNOLOGY, INC ]
