74VHC139
DUAL 2 TO 4 DECODER/DEMULTIPLEXER
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5.0 ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 139
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHC139MTR
74VHC139TTR
DESCRIPTION
The 74VHC139 is an advanced high-speed
CMOS DUAL 2 TO 4 LINE DECODER/
DEMULTIPLEXER fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.
The active low enable input can be used for gating
or as a data input for demultiplexing applications.
While the enable input is held high, all four outputs
are high independently of the other inputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 4
1/12
STMICROELECTRONICS [ STMICROELECTRONICS ]
