HCC/HCF4027B
DUAL-J-K MASTER-SLAVE FLIP-FLOP
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SET-RESET CAPABILITY
STATIC FLIP-FLOP OPERATION - RETAINS
STATE INDEFINITELY WITH CLOCK LEVEL
EITHER ”HIGH” OR ”LOW”
MEDIUM SPEED OPERATION - 16MHz (typ.
clock toggle rate at 10V)
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
0
TATIVE STANDARD N . 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”.
EY
(Plastic Package)
F
(Ceramic Frit Seal Package)
M1
(Micro Package)
C1
(Plastic Chip Carrier)
ORDER CODES :
HCC4027BF
HCF4027BM1
HCF4027BEY
HCF4027BC1
PIN CONNECTIONS
DESCRIPTION
The
HCC4027B
(extended temperature range) and
HCF4027B
(intermediate temperature range) are
monolithic integrated circuit, available in 16-lead
dual in-line plastic or ceramic package and plastic
micro package.
The
HCC/HCF4027B
is a single monolithic chip in-
tegrated circuit containing two identical complemen-
tary-symmetry J-K master-slave flip-flops. Each
flip-flop has provisions for individual J, K, Set, Reset,
and Clock input signals, Buffered Q and Q signals
are provided as outputs. This input-output arrange-
ment provides for compatible operation with the
HCC/HCF4013B
dual D-type flip-flop.
The
HCC/HCF4027B
is useful in performing control,
register, and toggle functions. Logic levels present
at the J and K inputs along with internal self-steering
control the state of each flip-flop ; changes in the flip-
flop state are synchronous with the positive-going
transition of the clock pulse. Set and reset functions
are independent of the clock and are initiated when
a high level signal is present at either the Set or
Reset input.
June 1989
1/12
STMICROELECTRONICS [ STMICROELECTRONICS ]
