Application Information
L6726A
9.2
Output capacitors
Output capacitors choice depends on the application constraints in point of output voltage
ripple and output voltage deviation during a load transient.
During steady-state conditions, the output voltage ripple is influenced by ESR and
capacitance of the output capacitors as follows:
ΔV
OUT_ESR
=
ΔI
L
⋅
ESR
1
-
ΔV
OUT_C
=
ΔI
L
⋅
--------------------------------------
8
⋅
C
OUT
⋅
F
SW
Where
ΔI
L
is the inductor current ripple. These contribution are not in phase, so total ripple
will be lower than the sum of their moduli. Even ESL and board parasitic inductance can
contribute significantly to output ripple.
During a load variation, the output capacitors supply to the load the additional current or
absorb the current in excess delivered by the inductor until converter reaction is completed.
In fact, even if the controller react immediately to the load transient saturating the duty cycle
to 80% or 0%, the current slew rate is limited by the inductance. At first approximation,
output voltage drop, based on ESR and capacitor charge/discharge and considering an
ideal load-step, can be estimated as follows:
ΔV
OUT_ESR
=
ΔI
OUT
⋅
ESR
L
⋅ ΔI
OUT
= -------------------------------------
-
2
⋅
C
OUT
⋅ ΔV
L
2
ΔV
OUT_C
Where
ΔV
L
is the voltage applied to the inductor during the transient (
D
MAX
⋅
V
IN
–
V
OUT
for
the load appliance or V
OUT
for the load removal).
MLCC capacitors typically have low ESR to minimize the ripple but also have low
capacitance that do not minimize the capacitive voltage deviation during load transient. On
the contrary, electrolytic capacitors usually have higher capacitance to minimize capacitive
voltage deviation during load transient, but also higher ESR value resulting in higher ripple
voltage and resistive voltage drop. For these reasons, a mix between electrolytic and MLCC
capacitor is usually suggested to minimize ripple as well as reducing voltage deviation in
dynamic conditions.
9.3
Input capacitors
The input capacitor bank is designed mainly to stand input rms current, which depends on
output current (I
OUT
) and duty-cycle (D) for the regulation as follows:
I
rms
=
I
OUT
⋅
D
⋅ (
1
–
D
)
The equation reaches its maximum value, I
OUT
/2, when D = 0.5. Losses depend on input
capacitor ESR:
P
=
ESR
⋅
I
rms
2
22/35
Doc ID 12754 Rev 4
STMICROELECTRONICS [ STMICROELECTRONICS ]
