欢迎访问ic37.com |
会员登录 免费注册
发布采购

M24C02-WDS6TG 参数 Datasheet PDF下载

M24C02-WDS6TG图片预览
型号: M24C02-WDS6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 16Kbit的, 8Kbit , 4k位, 2Kbit和1K位,串行I²C总线EEPROM [16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 29 页 / 484 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
 浏览型号M24C02-WDS6TG的Datasheet PDF文件第1页浏览型号M24C02-WDS6TG的Datasheet PDF文件第2页浏览型号M24C02-WDS6TG的Datasheet PDF文件第3页浏览型号M24C02-WDS6TG的Datasheet PDF文件第5页浏览型号M24C02-WDS6TG的Datasheet PDF文件第6页浏览型号M24C02-WDS6TG的Datasheet PDF文件第7页浏览型号M24C02-WDS6TG的Datasheet PDF文件第8页浏览型号M24C02-WDS6TG的Datasheet PDF文件第9页  
M24C16, M24C08, M24C04, M24C02, M24C01
SUMMARY DESCRIPTION
These I
2
C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 2048/1024/512/256/128 x 8 (M24C16,
M24C08, M24C04, M24C02, M24C01).
Figure 2. Logic Diagram
When writing data to the memory, the device in-
serts an acknowledge bit during the 9
th
bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 1. Signal Names
E0, E1, E2
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
VCC
3
E0-E2
SCL
WC
M24Cxx
SDA
SDA
SCL
WC
V
CC
V
SS
VSS
AI02033
I
2
C uses a two wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I
2
C bus definition.
The device behaves as a slave in the I
2
C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and RW bit (as described in
terminated by an acknowledge bit.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until V
CC
has reached
the POR threshold value, and all operations are
disabled – the device will not respond to any com-
mand. In the same way, when V
CC
drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command.
A stable and valid V
CC
(as defined in
and
must be applied before applying any log-
ic signal.
Figure 3. DIP, SO, TSSOP and MLP Connections (Top View)
M24Cxx
16Kb /8Kb /4Kb /2Kb /1Kb
NC / NC / NC / E0 / E0
NC / NC / E1 / E1 / E1
NC / E2 / E2 / E2 / E2
VSS
1
2
3
4
8
7
6
5
VCC
WC
SCL
SDA
AI02034E
Note: 1. NC = Not Connected
2. See
section for package dimensions, and how to identify pin-1.
4/29