M25P40
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25P40 boasts the
following data protection mechanisms:
■
Power-On Reset and an internal timer (t
PUW
)
can provide protection against inadvertant
changes while the power supply is outside the
operating specification.
■
Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
■
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit . This bit is returned to its reset state
by the following events:
– Power-up
– Write Disable (WRDI) instruction
completion
Table 2. Protected Area Sizes
Status Register
Content
BP2
Bit
0
0
0
0
1
1
1
1
BP1
Bit
0
0
1
1
0
0
1
1
BP0
Bit
0
1
0
1
0
1
0
1
none
Upper eighth (Sector 7)
Upper quarter (two sectors: 6 and 7)
Upper half (four sectors: 4 to 7)
All sectors (eight sectors: 0 to 7)
All sectors (eight sectors: 0 to 7)
All sectors (eight sectors: 0 to 7)
All sectors (eight sectors: 0 to 7)
Protected Area
Memory Content
Unprotected Area
All sectors
1
(eight sectors: 0 to 7)
Lower seven-eighths (seven sectors: 0 to 6)
Lower three-quarters (six sectors: 0 to 5)
Lower half (four sectors: 0 to 3)
none
none
none
none
–
■
■
■
Write Status Register (WRSR) instruction
completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
The Block Protect (BP2, BP1, BP0) bits allow
part of the memory to be configured as read-
only. This is the Software Protected Mode
(SPM).
The Write Protect (W) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be
protected. This is the Hardware Protected
Mode (HPM).
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one particular
instruction (the Release from Deep Power-
down instruction).
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
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