Operating modes
M48Z35, M48Z35Y
2.2
Write mode
The M48Z35/Y is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
from Chip Enable or t
from WRITE Enable
EHAX
WHAX
prior to the initiation of another READ or WRITE cycle. Data-in must be valid t
prior to
DVWH
the end of WRITE and remain valid for t
afterward. G should be kept high during
WHDX
WRITE cycles to avoid bus contention; although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs t
after W falls.
WLQZ
Figure 6.
Write enable controlled, write AC waveforms
tAVAV
A0-A14
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 7.
Chip enable controlled, write AC waveforms
tAVAV
A0-A14
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
10/23
STMICROELECTRONICS [ ST ]
