M50FLW080A, M50FLW080B
Table 6. FWH Bus Read Field Definitions
Clock
Cycle
Number Count
Clock
Cycle
FWH0- Memory
Field
Description
FWH3
I/O
On the rising edge of CLK with FWH4 Low, the contents of FWH0-
FWH3 indicate the start of a FWH Read cycle.
1
2
1
1
START
1101b
I
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the FWH
Flash Memory pins to select which FWH Flash Memory is being
addressed.
IDSEL
ADDR
MSIZE
XXXX
XXXX
I
I
I
A 28-bit address is transferred, with the most significant nibble
first. For the multi-byte read operation, the least significant bits
(MSIZE of them) are treated as Don't Care, and the read operation
is started with each of these bits reset to 0. Address lines A20-21
and A23-27 are treated as Don’t Care during a normal memory
array access, with A22=1, but are taken into account for a register
access, with A22=0. (See Table 15.)
3-9
10
7
1
This one clock cycle is driven by the host to determine the number
of Bytes that will be transferred. M50FLW080 supports: single
Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer
(0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b).
XXXX
1111b
The host drives FWH0-FWH3 to 1111b to indicate a turnaround
cycle.
11
12
1
1
TAR
TAR
I
1111b
(float)
The FWH Flash Memory takes control of FWH0-FWH3 during this
cycle.
O
The FWH Flash Memory drives FWH0-FWH3 to 0101b (short
wait-sync) for two clock cycles, indicating that the data is not yet
available. Two wait-states are always included.
13-14
15
2
1
WSYNC 0101b
RSYNC 0000b
O
O
O
The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating
that data will be available during the next clock cycle.
Data transfer is two CLK cycles, starting with the least significant
nibble. If multi-Byte read operation is enabled, repeat cycle-16 and
MSIZE
16-17
M=2n
DATA
XXXX
1111b
cycle-17 n times, where n = 2
.
previous
+1
The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate
a turnaround cycle.
1
1
TAR
TAR
O
previous
+1
1111b
(float)
The FWH Flash Memory floats its outputs, the host takes control
of FWH0-FWH3.
N/A
Figure 7. FWH Bus Read Waveforms
CLK
FWH4
FWH0-FWH3
START
1
IDSEL
1
ADDR
7
MSIZE
1
TAR
2
SYNC
3
DATA
M
TAR
2
Number of
clock cycles
AI08433B
14/53
STMICROELECTRONICS [ ST ]
