M50FLW080A, M50FLW080B
Figure 2. Logic Diagram (FWH/LPC Interface)
VCC VPP
4
ID0-ID3
5
GPI0-
GPI4
FWH4/LFRAME
CLK
IC
RP
INIT
M50FLW080A
M50FLW080B
FWH0/LAD0
FWH3/LAD3
WP
TBL
4
Table 1. Signal Names (FWH/LPC Interface)
FWH0/LAD0-
FWH3/LAD3
FWH4/
LFRAME
ID0-ID3
GPI0-GPI4
IC
RP
INIT
CLK
TBL
WP
RFU
Input/Output Communications
Input Communication Frame
Identification Inputs
(ID0 and ID1 are Reserved for
Future Use (RFU) in LPC mode)
General Purpose Inputs
Interface Configuration
Interface Reset
CPU Reset
Clock
Top Block Lock
Write Protect
Reserved for Future Use. Leave
disconnected
Supply Voltage
Optional Supply Voltage for Fast
Program and Erase Operations
Ground
Not Connected Internally
VSS
AI09229B
V
CC
V
PP
Figure 3. Logic Diagram (A/A Mux Interface)
V
SS
NC
VCC VPP
11
A0-A10
8
DQ0-DQ7
Table 2. Signal Names (A/A Mux Interface)
IC
A0-A10
DQ0-DQ7
G
Interface Configuration
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
Row/Column Address Select
Interface Reset
Supply Voltage
Optional Supply Voltage for Fast
Program and Erase Operations
Ground
Not Connected Internally
RC
IC
G
W
RP
M50FLW080A
M50FLW080B
W
RC
RP
V
CC
V
PP
V
SS
VSS
AI09230B
NC
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