M74HC161
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
2
3, 4, 5, 6
7
10
9
14, 13, 12,
11
15
8
16
SYMBOL
CLEAR
CLOCK
A, B, C, D
PE
TE
LOAD
QA to QD
CARRY
GND
Vcc
NAME AND FUNCTION
Asynchronous Master
Reset
Clock Input (LOW to
HIGH, Edge-triggered)
Data Inputs
Count Enable Input
Count Enable Carry Input
Parallel Enable Input
Flip Flop Outputs
Terminal Count Output
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
CLEAR
L
H
H
H
H
H
LOAD
X
L
H
H
H
X
PE
X
X
X
L
H
X
TE
X
X
L
X
H
X
CLOCK
X
QA
L
A
OUTPUTS
FUNCTION
QB
L
B
QC
L
C
QD
L
D
RESET TO "0"
PRESET DATA
NO COUNT
NO COUNT
COUNT
NO COUNT
NO CHANGE
NO CHANGE
COUNT UP
NO CHANGE
X : Don’t Care
A, B, C, D : Logic level of data inputs
Carry : CARRY = TE·Q
A
·Q
B
·Q
C
·Q
D
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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