M54HC279
M74HC279
QUAD S - R LATCH
.
.
.
.
.
.
.
.
HIGH SPEED
t
PD
= 12 ns (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 2
µA
(MAX.) AT T
A
= 25
°C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS279
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC279F1R
M74HC279M1R
M74HC279B1R
M74HC279C1R
PIN CONNECTIONS
(top view)
DESCRIPTION
The M54/74HC279 is a high speed CMOS QUAD S
- R LATCH fabricated in silicon gate C
2
MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
NC =
No Internal
Connection
March 1993
1/10
STMICROELECTRONICS [ STMICROELECTRONICS ]
