M54HC280
M74HC280
9 BIT PARITY GENERATOR
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HIGH SPEED
t
PD
= 22 ns (TYP.) at V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 4
µA
(MAX.) at T
A
= 25
°C
6 V
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
PIN AND FUNCTION COMPATIBLE WITH
54/74LS280
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC280F1R
M74HC280M1R
M74HC280B1R
M74HC280C1R
PIN CONNECTIONS
(top view)
DESCRIPTION
The M54/74HC280 is a high speed CMOS 9-BIT
PARITY GENERATOR fabricated in silicon gate
C
2
MOS technology. It has the same high speed per-
formance of LSTTL combined with true CMOS low
consumption.
It is composed of nine data inputs (A to I) and
odd/even parity outputs (Σ ODD and
Σ
EVEN). The
nine data inputs control the output conditions. When
the number of high level inputs is odd,
ΣODD
output
is kept high and
ΣEVEN
output low. Conversely,
when the number is even ,
ΣEVEN
output is kept
high and
ΣODD
low.
This IC generates either odd or even parity making
it flexible application.
The word-length capability is easily expanded by
cascading.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
October 1992
NC =
No Internal
Connection
1/10
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