ST92F124/F150/F250 - GENERAL DESCRIPTION
Figure 2. ST92F124V1: Architectural Block Diagram
FLASH
128 Kbytes
E
3 TM
1 Kbyte
RAM
4 Kbytes
256 bytes
Register File
8/16 bits
CPU
Interrupt
Management
ST9 CORE
MEMORY BUS
Ext. MEM.
ADDRESS
DATA
Port0
Ext. MEM.
ADDRESS
Ports
1,9
A[7:0]
D[7:0]
A[10:8]
A[21:11]
P0[7:0]
P1[7:3]
P1[2:0]
P2[7:0]
P3[7:4]
P3[3:1]
P4[7:4]
P4[3:0]
P5[7:0]
P6[5:2,0]
P6.1
P7[7:0]
P8[7:0]
P9[7:0]
SDA
SCL
AS
DS
RW
WAIT
NMI
DS2
RW
Fully
Prog.
I/Os
INT[6:0]
WKUP[15:0]
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
CK_AF
STOUT
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
V
REG
RCCU
I
2
C BUS
REGISTER BUS
ST. TIMER
WATCHDOG
WDOUT
HW0SW1
MISO
MOSI
SCK
SS
AV
DD
AV
SS
AIN[15:8]
AIN[7:0]
EXTRG
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
RDI
TDO
EF TIMER 0
SPI
EF TIMER 1
ADC
MF TIMER 0
SCI M
MF TIMER 1
SCI A
VOLTAGE
REGULATOR
The alternate functions (Italic
characters)
are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8 and Port9.
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