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STM32F103VET6 参数 Datasheet PDF下载

STM32F103VET6图片预览
型号: STM32F103VET6
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度高性能线 [High-density performance line]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 130 页 / 1933 K
品牌: STMICROELECTRONICS [ ST ]
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STM32F103xC, STM32F103xD, STM32F103xE  
Electrical characteristics  
5.3.17  
Communications interfaces  
I2C interface characteristics  
Unless otherwise specified, the parameters given in Table 51 are derived from tests  
performed under ambient temperature, f  
frequency and V supply voltage conditions  
PCLK1  
DD  
summarized in Table 10.  
The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG  
2
2
I
performance line C interface meets the requirements of the standard I C communication  
protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not  
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O  
pin and V is disabled, but is still present.  
DD  
2
The I C characteristics are described in Table 51. Refer also to Section 5.3.14: I/O port  
for more details on the input/output alternate function characteristics (SDA  
characteristics  
and SCL)  
.
2
Table 51. I C characteristics  
Standard mode I2C(1)  
Fast mode I2C(1)(2)  
Symbol  
Parameter  
Unit  
Min  
Max  
Min  
Max  
tw(SCLL)  
tw(SCLH)  
tsu(SDA)  
th(SDA)  
SCL clock low time  
SCL clock high time  
SDA setup time  
4.7  
4.0  
1.3  
0.6  
µs  
250  
0(3)  
100  
0(4)  
SDA data hold time  
900(3)  
300  
tr(SDA)  
tr(SCL)  
ns  
SDA and SCL rise time  
1000  
300  
20 + 0.1Cb  
tf(SDA)  
tf(SCL)  
SDA and SCL fall time  
Start condition hold time  
300  
th(STA)  
tsu(STA)  
4.0  
4.7  
4.0  
4.7  
0.6  
0.6  
0.6  
1.3  
µs  
Repeated Start condition  
setup time  
tsu(STO)  
Stop condition setup time  
μs  
μs  
Stop to Start condition time  
(bus free)  
tw(STO:STA)  
Capacitive load for each bus  
line  
Cb  
400  
400  
pF  
Guaranteed by design, not tested in production.  
1.  
2. fPCLK1 must be higher than 2 MHz to achieve standard mode I2C frequencies. It must be higher than 4 MHz  
to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast  
mode maximum clock speed of 400 kHz.  
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low  
period of SCL signal.  
3.  
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the  
undefined region of the falling edge of SCL.  
4.  
Doc ID 14611 Rev 8  
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