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STM8S105C4B3 参数 Datasheet PDF下载

STM8S105C4B3图片预览
型号: STM8S105C4B3
PDF下载: 下载PDF文件 查看货源
内容描述: 接入线路, 16兆赫STM8S 8位MCU ,最多32 KB闪存,集成的EEPROM , 10位ADC ,定时器, UART , SPI , I²C [Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C]
分类和应用: 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 127 页 / 1323 K
品牌: STMICROELECTRONICS [ ST ]
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Product overview  
STM8S105xx  
The UBC area remains write-protected during in-application programming. This means that  
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot  
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the  
IAP and communication routines.  
Figure 2: Flash memory organisation  
Data memory area ( 1 Kbyte)  
Option bytes  
Data  
EEPROM  
memory  
Programmable area  
from 1 Kbyte  
(2 first pages) up to  
UBC area  
Remains write protected during IAP  
32 Kbytes  
(1 page steps)  
Medium density  
Flash program memory  
(up to 32 Kbytes)  
Program memory area  
Write access possible for IAP  
Read-out protection (ROP)  
The read-out protection blocks reading and writing the Flash program memory and data  
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,  
any attempt to toggle its status triggers a global erase of the program and data memory. Even  
if no protection can be considered as totally unbreakable, the feature provides a very high  
level of protection for a general purpose microcontroller.  
4.5  
Clock controller  
The clock controller distributes the system clock (fMASTER) coming from different oscillators  
to the core and the peripherals. It also manages clock gating for low power modes and ensures  
clock robustness.  
Features  
Clock prescaler: To get the best compromise between speed and current consumption  
the clock frequency to the CPU and peripherals can be adjusted by a programmable  
prescaler.  
Safe clock switching: Clock sources can be changed safely on the fly in run mode  
through a configuration register. The clock signal is not switched until the new clock source  
is ready. The design guarantees glitch-free switching.  
Clock management: To reduce power consumption, the clock controller can stop the  
clock to the core, individual peripherals or memory.  
Master clock sources: Four different clock sources can be used to drive the master  
clock:  
1-16 MHz high-speed external crystal (HSE)  
-
Up to 16 MHz high-speed user-external clock (HSE user-ext)  
-
14/127  
DocID14771 Rev 9