STP3NB100
STP3NB100FP
N - CHANNEL 1000V - 5.3
Ω
- 3 A - TO-220/TO-220FP
PowerMESH™ MOSFET
TARGET DATA
TYPE
ST P3NB100
ST P3NB100FP
s
s
s
s
s
V
DSS
1000 V
1000 V
R
DS(on)
< 6
Ω
< 6
Ω
I
D
3 A
3 A
TYPICAL R
DS(on)
= 5.3
Ω
EXTREMELY HIGH dv/dt CAPABILITY
100% AVALANCHE TESTED
VERY LOW INTRINSIC CAPACITANCES
GATE CHARGE MINIMIZED
3
1
2
3
1
2
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an
advanced family of power MOSFETs with
outstanding performances. The new patent
pending strip layout coupled with the Company’s
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SWITCH MODE POWER SUPPLIES (SMPS)
s
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(•)
P
tot
dv/dt(
1
)
V
ISO
T
s tg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 kΩ)
G ate-source Voltage
Drain Current (continuous) at T
c
= 25 C
Drain Current (continuous) at T
c
= 100 C
Drain Current (pulsed)
T otal Dissipation at T
c
= 25 C
Derating Factor
Peak Diode Recovery voltage slope
Insulation W ithstand Voltage (DC)
Storage Temperature
Max. Operating Junction Temperature
o
o
o
TO-220
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
Value
ST P3NB100 STP3NB100F P
1000
1000
±
30
3
1.9
12
100
0.8
4.5
-65 to 150
150
(
1
) I
SD
≤ 3 Α,
di/dt
≤
200 A/
µ
s, V
DD
≤
V
(BR)DSS
, Tj
≤
T
JMAX
Un it
V
V
V
3(**)
1.1
12
35
0.28
4.5
2000
A
A
A
W
W/ C
V/ns
V
o
o
o
C
C
(
•
) Pulse width limited by safe operating area
(
**) Limited only by T
MAX
October 1998
1/6
STMICROELECTRONICS [ STMICROELECTRONICS ]
