TSA1201 APPLICATION NOTE
DETAILED INFORMATION
corrected data are outputed through the digital
buffers.
Signal input is sampled on the rising edge of the
clock while digital outputs are delivered on the
falling edge of the clock.
The advantages of such a converter reside in the
combination of pipeline architecture and the most
advanced technologies. The highest dynamic
performances are achieved while consumption
remains at the lowest level.
Some functionalites have been added in order to
simplify as much as possible the application
board. These operational modes are described in
the following table.
The TSA1201 is a High Speed analog to digital
converter based on a pipeline architecture and the
latest deep submicron CMOS process to achieve
the best performances in terms of linearity and
power consumption.
The pipeline structure consists of 11 internal
conversion stages in which the analog signal is
fed and sequencially converted into digital data.
Each 10 first stages consists of an Analog to
Digital converter, a Digital to Analog converter, a
Sample and Hold and a gain of 2 amplifier. A
1.5-bit conversion resolution is achieved in each
stage. The latest stage simply is a comparator.
Each resulting LSB-MSB couple is then time
shifted to recover from the delay caused by
conversion. Digital data correction completes the
processing by recovering from the redundancy of
the (LSB-MSB) couple for each stage. The
The TSA1201 is pin to pin compatible with the
8bits/40Msps TSA0801, the 10bits/25Msps
TSA1001 and the 10bits/50Msps TSA1002. This
ensures a conformity with the product family and
above all, an easy upgrade of the application
OPERATIONAL MODES DESCRIPTION
Inputs
Outputs
Analog input differential level
DFSB OEB SRC OR DR Most Significant Bit (MSB)
(VIN-VINB)
-RANGE
>
>
RANGE
H
H
H
L
L
L
L
L
L
L
H
X
X
X
X
X
X
X
X
X
H
L
H
H
L
CLK
CLK
CLK
CLK
CLK
CLK
D11
D11
(VIN-VINB)
RANGE> (VIN-VINB) >-RANGE
D11
(VIN-VINB)
-RANGE
>
>
RANGE
H
H
L
D11 Complemented
D11 Complemented
D11 Complemented
HZ
(VIN-VINB)
L
RANGE> (VIN-VINB) >-RANGE
L
X
X
X
X
X
X
HZ HZ
X
X
CLK 25Msps compliant slew rate
CLK 50Msps compliant slew rate
Data Format Select (DFSB)
Output Enable (OEB)
When set to low level (VIL), the digital input DFSB
When set to low level (VIL), all digital outputs
remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state while the
converter goes on sampling. When OEB is set to a
low level again, the data are then present on the
output with a very short Ton delay.
provides a two’s complement digital output MSB.
This can be of interest when performing some
further signal processing.
When set to high level (VIH), DFSB provides a
standard binary output coding.
Therefore, this allows the chip select of the device.
The timing diagram summarizes this functionality.
12/20
STMICROELECTRONICS [ ST ]
