Features
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First-in first-out dual port memory
16384 x 9 organization
Fast Flag and access times: 15, 30ns
Wide temperature range: - 55
°C
to + 125
°C
Fully expandable by word width or depth
Asynchronous read/write operations
Empty, full and half flags in single device mode
Retransmit capability
Bi-directional applications
Battery back-up operation: 2V data retention
TTL compatible
Single 5V + 10% power supply
QML Q and V with SMD 5962-93177
Description
The M67206F implements a first-in first-out algorithm, featuring asynchronous
read/write operations. The FULL and EMPTY flags prevent data overflow and under-
flow. The Expansion logic allows unlimited expansion in word size and depth with no
timing penalties. Twin address pointers automatically generate internal read and write
addresses, and no external address information is required. Address pointers are
automatically incremented with the write pin and read pin. The 9 bits wide data are
used in data communications applications where a parity bit for error checking is nec-
essary. The Retransmit pin resets the Read pointer to zero without affecting the write
pointer. This is very useful for retransmitting data when an error is detected in the
system.
Using an array of eight transistors (8 T) memory cell, the M67206F combines an
extremely low standby supply current (typ = 0.1
µA)
with a fast access time at 15 ns
over the full temperature range. All versions offer battery backup data retention capa-
bility with a typical power consumption at less than 2
µW.
The M67206F is processed according to the methods of the latest revision of the MIL
PRF 38535 (Q and V) or ESA SCC 9000.
Rad Tolerant
High Speed
16 K x 9
Parallel FIFO
M67206F
Rev. E–20-Aug-01
1
TEMIC [ TEMIC SEMICONDUCTORS ]
