Depth Expansion (Daisy
Chain) Mode
The M672061F can be easily adapted for applications which require more than 16384
words. Figure 5 demonstrates Depth Expansion using three M672061F. Any depth can
be achieved by adding additional 672061F.
The M672061F operates in the Depth Expansion configuration if the following conditions
are met:
1. The first device must be designated by connecting the First Load (FL) control
input to ground.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be connected to the Expansion In
(XI) pin of the next device. See Figure 5
4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag
(EF). This requires that all EF’s and all FFs be ØRed (i.e. all must be set to generate the
correct composite FF or EF). See Figure 5
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth
Expansion Mode.
Compound Expansion
Module
Bidirectional Mode
It is quite simple to apply the two expansion techniques described above together to cre-
ate large FIFO arrays (see Figure 6).
Applications which require data buffering between two systems (each system being
capable of Read and Write operations) can be created by coupling M672061F as shown
in Figure 7 Care must be taken to ensure that the appropriate flag is monitored by each
system (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device
on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.
Two types of flow-through modes are permitted : a read flow-through and a write flow-
through mode. In the read flow-through mode (Figure 18) the FIFO stack allows a single
word to be read after one word has been written to an empty FIFO stack. The data is
enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the
first write edge and remains on the bus until the R line is raised from low to high, after which the
bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating tem-
porary reset and then will be set. In the interval in which R is low, more words may be written to
the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag) ; how-
ever, the same word (written on the first write edge) presented to the output bus as the read
pointer will not be incremented if R is low. On toggling R, the remaining words written to the
FIFO will appear on the output bus in accordance with the read cycle timings.
In the write flow-through mode (Figure 19), the FIFO stack allows a single word of data
to be written immediately after a single word of data has been read from a full FIFO
stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again
in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading
edge of W. The W line must be toggled when FF is not set in order to write new data into the
FIFO stack and to increment the write pointer.
Data Flow - Through
Modes
9
M672061F
Rev. E–20-Aug-01
TEMIC [ TEMIC SEMICONDUCTORS ]
