80C154/83C154
(MSB)
TF2
(LSB)
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
The baud rate generator mode is selected by : RCLK = 1 and/or TCLK = 1.
Symbol
Position
Name and Significance
TF2
T2CON.7
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 OR TCLK = 1.
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software.
RCLK
TCLK
T2CON.5
T2CON.4
T2CON.3
Receive clock flag. When set, causes the serial port to use Timer2 overflow pulses for its
receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for
its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for
the transmit clock.
EXEN2
Timer 2 external enable flag. When set, allows capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
T2CON.1
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2
Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN 2 = 1. When cleared, auto reloads will occur either with Timer 2 overflows or
negative transition at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this
bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
Figure 9.
Timer Functions
Watchdog timer
In fact, timer 0 & 1 can be connected by a software
instruction to implement a 32 bit timer function. Timer 0
(mode 3) or timer 1 (mode 0, 1, 2) or a 32 bit timer
consisting of timer 0 + timer 1 can be employed in the
watchdog mode, in which case a CPU reset is generated
upon a TF1 flag.
The internal pull-up resistances at ports 1~3 can be set to
a ten times increased value simply by software.
32 bit timer [IOCON bit 6 (T32) = 1]
32 Bit Mode and Watching Mode
The 83C154 has two supplementary modes. They are
accessed by bits WDT and T32 of register IOCON. Figure
10 showns how IOCON must be programmed in order to
have access to these functions
MATRA MHS
9
Rev.F (14 Jan. 97)
TEMIC [ TEMIC SEMICONDUCTORS ]
