SLAS894A – MAY 2013 – REVISED AUGUST 2013
Ultra Low Power Stereo Audio Codec With Embedded miniDSP
Check for Samples:
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FEATURES
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following
Results:
– Device Temperature Grade 3: –40°C to 85°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Stereo Audio DAC with 100dB SNR
4.1mW Stereo 48ksps DAC Playback
Stereo Audio ADC with 93dB SNR
6.1mW Stereo 48ksps ADC Record
PowerTune™
Extensive Signal Processing Options
Embedded miniDSP
Six Single-Ended or Three Fully-Differential
Analog Inputs
Stereo Analog and Digital Microphone Inputs
Stereo Headphone Outputs
Stereo Line Outputs
Very Low-Noise PGA
Low Power Analog Bypass Mode
Programmable Microphone Bias
IN1_L
IN2_L
IN3_L
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2
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Programmable PLL
Integrated LDO
5 mm x 5 mm 32-pin QFN Package
APPLICATIONS
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Automotive
Portable Navigation Devices (PND)
Portable Media Player (PMP)
Mobile Handsets
Communication
Portable Computing
Acoustic Echo Cancellation (AEC)
Active Noise Cancellation (ANC)
Advanced DSP algorithms
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DESCRIPTION
The TLV320AIC3254-Q1 (also called the AIC3254-
Q1) is a flexible, low-power, low-voltage stereo audio
codec with programmable inputs and outputs,
PowerTune capabilities, fully-programmable miniDSP,
fixed predefined and parameterizable signal
processing blocks, integrated PLL, integrated LDOs
and flexible digital interfaces.
AGC
+
0…+47.5 dB
Left
ADC
+
0.5 dB
steps
-30...0 dB
DRC
DAC
Signal
Proc.
Vol . Ctrl
-72...0dB
-6...+29dB
+
1dB steps
-6...+29dB
+
LOL
HPL
t
pl
´
Gain Adj.
ADC
Signal
Proc.
´
Left
DAC
miniDSP
-30...0 dB
Data
Interface
miniDSP
1dB steps
-6...+29dB
+
LOR
+
IN3_R
IN2_R
IN1_R
0…
+47.5 dB
Right
ADC
t
pr
1dB steps
Gain Adj.
´
+
ADC
Signal
Proc.
AGC
DAC
Signal
Proc.
DRC
´
Right
DAC
-72...0dB
-6...+29dB
+
1dB steps
HPR
0.5 dB steps
Vol . Ctrl
SPI_Select
Reset
HPVdd
MicBias
SPI / I2C
Control Block
Mic
Bias
Ref
LDO in
PLL
Digital Interrupt Secondary
Mic.
Ctrl
I
2
S IF
Primary
I
2
S Interface
ALDO
Supplies
DLDO
WCLK
LDO Select
AVdd
DVdd
IOVdd
AVss
DVss
IOVss
SCL/SSZ
SDA/MOSI
MISO
SCLK
MCLK
GPIO
DOUT
DIN
BCLK
Pin Muxing/ Clock Routing
Ref
Figure 1. Simplified Block Diagram
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerTune is a trademark of Texas Instruments.
Copyright © 2013, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TI [ TEXAS INSTRUMENTS ]
