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SBAS366A – OCTOBER 2006 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
All specifications at T
A
= –40°C to +85°C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise noted.
ADS1230
PARAMETER
Analog Inputs
Full-Scale Input Voltage (AINP – AINN)
Common-Mode Input Range
Differential Input Current
System Performance
Resolution
No Missing Codes
Internal Oscillator, SPEED = High
Data Rate
Internal Oscillator, SPEED = Low
External Oscillator, SPEED = High
External Oscillator, SPEED = Low
Digital Filter Settling Time
Integral Nonlinearity (INL)
Input Offset Error
(1)
Input Offset Drift
Gain Error
Gain Drift
Normal-Mode Rejection
(2)
Common-Mode Rejection
Input-Referred Noise
Power-Supply Rejection
Voltage Reference Input
Voltage Reference Input (V
REF
)
Negative Reference Input (REFN)
Positive Reference Input (REFP)
Voltage Reference Input Current
Digital
V
IH
Logic Levels
V
IL
V
OH
V
OL
Input Leakage
External Clock Input Frequency (f
CLKIN
)
Serial Clock Input Frequency (f
SCLK
)
I
OH
= 1mA
I
OL
= 1mA
0 < V
IN
< DVDD
0.2
4.9152
All digital inputs except CLKIN
CLKIN
0.7 DVDD
0.7 DVDD
DGND
DVDD – 0.4
0.2 DVDD
±10
6
5
DVDD + 0.1
5.1
0.2 DVDD
V
V
V
V
V
μA
MHz
MHz
V
REF
= REFP – REFN
1.5
AGND – 0.1
REFN + 1.5
10
AVDD
AVDD + 0.1V
REFP – 1.5
AVDD + 0.1
V
V
V
nA
f
IN
= 50Hz or 60Hz ±1Hz,
f
DATA
= 10SPS
at DC, AVDD = 0.1V
f
DATA
= 10SPS
f
DATA
= 80SPS
at DC, AVDD = 0.1V
90
Internal Oscillator
External Oscillator
(3)
CONDITIONS
MIN
TYP
MAX
UNIT
±0.5V
REF
/PGA
AGND + 1.5V
±2
AVDD – 1.5V
V
V
nA
20
80
10
f
CLK
/61,440
f
CLK
/491,520
4
±10
±6
±3
±10
±0.8
±4
80
90
90
100
110
53
100
100
Bits
SPS
SPS
SPS
SPS
Conversions
ppm
ppm
ppm of FS
nV/°C
%
ppm/°C
dB
dB
dB
nV, rms
nV, rms
dB
Full Settling
Differential Input, End-Point Fit, G = 64
Differential Input, End-Point Fit, G = 128
(1)
(2)
(3)
Offset calibration can minimize these errors to the level of noise at any temperature.
Specification is assured by the combination of design and final production test.
External oscillator = 4.9152MHz.
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