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ADS5232IPAG 参数 Datasheet PDF下载

ADS5232IPAG图片预览
型号: ADS5232IPAG
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道, 12位, 65MSPS , + 3.3V模拟数字转换器 [Dual, 12-Bit, 65MSPS, +3.3V Analog-to-Digital Converter]
分类和应用: 转换器模数转换器
文件页数/大小: 29 页 / 743 K
品牌: TI [ TEXAS INSTRUMENTS ]
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Burr Brown Products
from Texas Instruments
SBAS294A – JUNE 2004 – REVISED MARCH 2006
Dual, 12-Bit, 65MSPS, +3.3V
Analog-to-Digital Converter
FEATURES
Single +3.3V Supply
High SNR: 70.7dBFS at f
IN
= 5MHz
Total Power Dissipation:
Internal Reference: 371mW
External Reference: 335mW
Internal or External Reference
Low DNL: ±0.3LSB
Flexible Input Range: 1.5V
PP
to 2V
PP
TQFP-64 Package
DESCRIPTION
The ADS5232 is a dual, high-speed, high dynamic
range, 12-bit pipelined analog-to-digital converter
(ADC). This converter includes a high-bandwidth
sample-and-hold amplifier that gives excellent
spurious performance up to and beyond the Nyquist
rate. The differential nature of the sample-and-hold
amplifier and ADC circuitry minimizes even-order
harmonics and gives excellent common-mode noise
immunity.
The ADS5232 provides for setting the full-scale range
of the converter without any external reference
circuitry. The internal reference can be disabled,
allowing low-drive, external references to be used for
improved tracking in multichannel systems.
The ADS5232 provides an over-range indicator flag
to indicate an input signal that exceeds the full-scale
input range of the converter. This flag can be used to
reduce the gain of front-end gain control circuitry.
There is also an output enable pin to allow for
multiplexing and testing on a PC board.
The ADS5232 employs digital error correction
techniques to provide excellent differential linearity for
demanding imaging applications. The ADS5232 is
available in a TQFP-64 package.
AV
DD
SDATA SEN SCLK SEL
V
DRV
OE
A
APPLICATIONS
Communications IF Processing
Communications Base Stations
Test Equipment
Medical Imaging
Video Digitizing
CCD Digitizing
ADS5232
Serial
Interface
DISABLE_PLL
IN
A
V
IN
IN
A
S/H
12-Bit
Pipelined
ADC
Error
Correction
Logic
3-State
Output
D11A
·
·
·
D0A
OVR
A
DV
A
INT/EXT
CM
REFT
REFB
DV
B
12-Bit
Pipelined
ADC
Error
Correction
Logic
D11B
Internal
Reference
Timing/Duty Cycle
Adjust (PLL)
CLK
IN
B
VIN
S/H
IN
B
3-State
Output
·
·
·
D0B
OVR
B
STPD
OE
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2006, Texas Instruments Incorporated