ADS8317
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SBAS356A–JUNE 2007–REVISED SEPTEMBER 2007
THEORY OF OPERATION
The digital data that are provided on the DOUT pin are
for the conversion currently in progress—there is no
pipeline delay. It is possible to continue to clock the
ADS8317 after the conversion is complete and to
obtain the serial data least significant bit first. See the
Digital Timing section for more information.
The ADS8317 is a classic Successive Approximation
Register (SAR) analog-to-digital (A/D) converter. The
architecture is based on capacitive redistribution that
inherently includes a sample-and-hold function. The
converter is fabricated on a 0.6μ CMOS process. The
architecture and fabrication process allow the
ADS8317 to acquire and convert an analog signal at
up to 250,000 conversions per second while
ANALOG INPUT
consuming less than 10mW from VDD
.
The analog input is bipolar and fully differential. There
are two general methods of driving the analog input
of the ADS8317: single-ended or differential, as
shown in Figure 37. When the input is single-ended,
the –IN input is held at a fixed voltage. The +IN input
swings around the same voltage and the
peak-to-peak amplitude is 2 × VREF. The value of
VREF determines the range over which the common
voltage may vary, as shown in Figure 39 and
Figure 38.
Differential linearity for the
ADS8317
is
factory-adjusted via a package-level trim procedure.
The state of the trim elements is stored in non-volatile
memory and is continuously updated after each
acquisition cycle, just prior to the start of the
successive approximation operation. This process
ensures that one complete conversion cycle always
returns the part to its factory-adjusted state in the
event of a power interruption.
The ADS8317 requires an external reference, an
external clock, and a single power source (VDD). The
external reference can be any voltage between 0.1V
and VDD/2. The value of the reference voltage directly
sets the range of the analog input. The reference
input current depends on the conversion rate of the
ADS8317.
Single-Ended Input
2 ´ VREF
ADS8317
Peak-to-Peak
Common
Voltage
The external clock can vary between 24kHz (1kHz
throughput) and 6.0MHz (250kHz throughput). The
duty cycle of the clock is not significant, as long as
the minimum high and low times are at least 200ns
(VDD = 4.75V or greater). The minimum clock
frequency is set by the leakage on the internal
capacitors to the ADS8317.
Differential Input
VREF
Peak-to-Peak
ADS8317
Common
VREF
Voltage
Peak-to-Peak
The analog input is provided to two input pins: +IN
and –IN. When
a conversion is initiated, the
differential input on these pins is sampled on the
internal capacitor array. While a conversion is in
progress, both inputs are disconnected from any
internal function.
Figure 37. Methods of Driving the
ADS8317—Single-Ended or Differential
The digital result of the conversion is clocked out by
the DCLOCK input and is provided serially (most
significant bit first) on the DOUT pin.
16
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