SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007
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TIMING INFORMATION
t
CYC
CS/SHDN
Sample
t
SUCS
DCLOCK
t
CSD
D
OUT
Conversion
Power Down
Use positive clock edge for data transfer
Hi-Z
0
B15 B14 B13 B12 B11 B10 B9 B8
(MSB)
t
CONV
B7
B6
B5 B4
B3
B2
B1 B0
(LSB)
(1)
Hi-Z
t
SMPL
NOTE: (1) A minimum of 22 clock cycles are required for 16-bit conversion; 24 clock cycles are shown.
If CS remains low at the end of conversion, a new data stream is shifted out with LSB-first data followed by zeroes indefinitely.
t
CYC
CS/SHDN
t
SUCS
DCLOCK
t
CSD
D
OUT
Hi-Z
Null
Bit
Power Down
B15 B14 B13 B12 B11 B6
(MSB)
B5
B4
B3
B2
B1
t
SMPL
t
CONV
B0 B1
(LSB)
B2
B3
B4
B5
B0
B11 B12 B13 B14 B15
(MSB)
(2)
Hi-Z
NOTE: (2) After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeroes indefinitely.
1.4V
3kW
D
OUT
100pF
C
LOAD
Test Point
D
OUT
t
r
t
f
90%
10%
Voltage Waveforms for D
OUT
Rise and Fall Times, t
r
, t
f
Load Circuit for t
dDO
, t
r
, and t
f
Test Point
DCLOCK
t
dDO
D
OUT
t
hDO
Voltage Waveforms for D
OUT
Delay Times, t
dDO
D
OUT
3kW
100pF
C
LOAD
Load Circuit for t
dis
and t
en
V
DD
t
dis
Waveform 2, t
en
t
dis
Waveform 1
CS/SHDN
90%
CS/SHDN
D
OUT
Waveform 1
(3)
t
dis
D
OUT
Waveform 2
(4)
Voltage Waveforms for t
dis
90%
DCLOCK
1
4
5
10%
D
OUT
t
en
Voltage Waveforms for t
en
B15
NOTES: (3) Waveform 1 is for an output with internal conditions such that
the output is high unless disabled by the output control.
(4) Waveform 2 is for an output with internal conditions such that
the output is low unless disabled by the output control.
Figure 1. Timing Diagrams
8
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