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SLUS732 – SEPTEMBER 2006
SMBus TIMING SPECIFICATIONS (continued)
V
DD
= 3 V to 3.6 V, T
A
= -20°C to 85°C unless otherwise noted
PARAMETER
t
(HIGH)
t
LOW:SEXT)
t
LOW:MEXT
t
f
t
r
(2)
(3)
(4)
Clock high period
Cumulative clock low slave extend time
Cumulative clock low master extend time
Clock/data fall time
Clock/data rise time
See
See
See
(2)
(3)
(4)
TEST CONDITIONS
MIN
4
TYP MAX
50
25
10
300
1000
UNIT
µs
ms
ms
ns
ns
(V
ILMAX
– 0.15 V) to (V
IHMIN
+ 0.15 V)
0.9 V
DD
to (V
ILMAX
– 0.15 V)
t
(HIGH)
Max. is minimum bus idle time. SMBC = 1 for t > 50 ms causes reset of any transaction involving bq2084-V143 that is in
progress.
t
(LOW:SEXT)
is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
t
(LOW:MEXT)
is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
SMBus TIMING DIAGRAMS
5
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