CC2520 DATASHEET
2.4 GHZ IEEE 802.15.4/ZIGBEE® RF TRANSCEIVER
SWRS068 – DECEMBER 2007
11 GPIO
CC2520 has 6 GPIO pins that can be individually configured as inputs, outputs and activate pull-up
resistors. Each GPIO has an associated register, GPIOCTRLn, where the MSB configure the pin to either
input or output. The GPIOCTRL register control pull-up for each individual GPIO pin, extra drive strength for
all pins and analog function for pin 0 and 1. See section 30 for details about test functionality and
observability through GPIO.
Note that GPIO5, which is configured as an input in LPM2, should be tied either to ground or VDD when
entering LPM2. If GPIO5 (or any other input) is left floating, the current consumption will be unpredictable.
11.1 Reset Configuration of GPIO Pins
The reset setting for GPIO pins are as shown in the table below. This is also the configuration that is used
when the device is in LPM2. If a different GPIO setup is required, the GPIOs have to be re-configured every
time CC2520 has been in LPM2.
This particular reset configuration was selected so that CC2520 looks as much like CC2420 as possible.
Table 8: GPIO reset state
GPIO Dir
pin
0
1
2
Out
Out
Out
Value Pull
up
0
0
0
No
No
No
Extra
drive
No
No
No
Polarity
Positive
Positive
Positive
Signal
clock
fifo
fifop
GPIOCTRLn
value (hex)
0x00
0x27
0x28
Description
1MHz clock signal with 50/50 duty cycle.
High when one or more bytes are in the RX FIFO.
Low during RX FIFO overflow.
High when the number of bytes in the RX FIFO
exceeds the programmable threshold or at least one
complete frame is in the RX FIFO. Also high during
RX FIFO overflow.
Clear channel assessment. See FSMSTAT1 register
for details on how to configure the behavior of this
signal.
Pin is high when SFD has been received or
transmitted. Cleared when leaving RX/TX
respectively.
No function
3
Out
0
No
No
Positive
cca
0x29
4
Out
0
No
No
Positive
sfd
0x2A
5
In
Tie to No
ground
or VDD
No
Positive
0x90
11.2 GPIO as Input
When configured as input, the GPIO pin can be used to trigger one of 16 different command strobes (See
section 15) as shown in the GPIO configuration table in section 12.6. These command strobes are a subset
of all the SPI instructions available. The command strobe is triggered by applying a rising or falling edge to
the GPIO pin depending on the setting in the GPIOPOLARITY register. Which command strobe the pin
triggers is set by the 7 LSBs in GPIOCTRLn.
Example:
Set up GPIO2 to run SACK instruction on rising edge.
•
•
Set GPIOPOLARITY[2] to ‘1’. GPIO pin 2 set to rising edge active.
Set GPOICTRL2[7:0] to “1000 0101” . GPIO pin 2 is now an input and connected to the SACK
instruction.
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