CDC2536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS377D – APRIL 1994 – REVISED OCTOBER 1998
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Low Output Skew for Clock-Distribution
and Clock-Generation Applications
Operates at 3.3-V V
CC
Distributes One Clock Input to Six Outputs
One Select Input Configures Three Outputs
to Operate at One-Half or Double the Input
Frequency
No External RC Network Required
On-Chip Series Damping Resistors
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
Application for Synchronous DRAM,
High-Speed Microprocessor
TTL-Compatible Inputs and Outputs
Outputs Drive 50-Ω Parallel-Terminated
Transmission Lines
State-of-the-Art
EPIC-
ΙΙ
B
™
BiCMOS Design
Significantly Reduces Power Dissipation
Distributed V
CC
and Ground Pins Reduce
Switching Noise
Packaged in Plastic 28-Pin Shrink
Small-Outline Package
DB PACKAGE
(TOP VIEW)
AV
CC
AGND
CLKIN
SEL
OE
GND
1Y1
V
CC
GND
1Y2
V
CC
GND
1Y3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
CC
AGND
FBIN
TEST
CLR
V
CC
2Y1
GND
V
CC
2Y2
GND
V
CC
2Y3
GND
description
The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to
precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is
specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from
50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536
operates at 3.3-V V
CC
and is designed to drive a 50-
W
transmission line. The CDC2536 also provides on-chip
series-damping resistors, eliminating the need for external termination components.
The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock
(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between
CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL)
input configures three Y outputs to operate at one-half or double the CLKIN frequency, depending on which pin
is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the
duty cycle at the input clock.
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state.
When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass
the PLL. TEST should be strapped to GND for normal operation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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