CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
25
MAX
50
UNIT
VCO is operating at four times the CLKIN/CLKIN frequency
VCO is operating at double the CLKIN/CLKIN frequency
f
Clock frequency
MHz
clock
50
100
60%
50
Input clock duty cycle
40%
After SEL1, SEL0
After OE↓
†
Stabilization time
50
µs
After power up
50
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 15 pF (see Note 4 and Figures 1, 2, and 3)
L
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
MIN
MAX
UNIT
Duty cycle
Y
45%
100
55%
f
MHz
ps
max
Jitter
CLKIN↑
CLKIN↑
Y↑
Y
200
500
0.5
1
(pk-pk)
‡
t
t
t
t
t
–500
ps
phase error
‡
Y
ns
sk(o)
‡
Y
ns
sk(pr)
1.4
1.4
ns
r
f
ns
‡
Thepropagationdelay,t
are only valid for equal loading of all outputs.
,isdependentonthefeedbackpathfromanyoutputtoFBIN.Thet
,t
,andt
specifications
sk(pr)
phaseerror
phaseerror sk(o)
NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
PARAMETER MEASUREMENT INFORMATION
2.4 V
1.6 V
CLKIN
2 V
2 V
CLKIN
t
phase error
V
V
OH
2 V
0.8 V
2 V
0.8 V
1.5 V
Output
From Output
Under Test
OL
500 Ω
C
= 15 pf
L
t
t
f
r
(see Note A)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT FOR OUTPUTS
NOTES: A.
B. The outputs are measured one at a time with one transition per measurement.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
C includes probe and jig capacitance.
L
O
r
f
Figure 1. Load Circuit and Voltage Waveforms
7
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