欢迎访问ic37.com |
会员登录 免费注册
发布采购

CDC2586PAH 参数 Datasheet PDF下载

CDC2586PAH图片预览
型号: CDC2586PAH
PDF下载: 下载PDF文件 查看货源
内容描述: 具有三态输出的3.3V锁相环时钟驱动器 [3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS]
分类和应用: 时钟驱动器逻辑集成电路输出元件信息通信管理
文件页数/大小: 12 页 / 167 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号CDC2586PAH的Datasheet PDF文件第2页浏览型号CDC2586PAH的Datasheet PDF文件第3页浏览型号CDC2586PAH的Datasheet PDF文件第4页浏览型号CDC2586PAH的Datasheet PDF文件第5页浏览型号CDC2586PAH的Datasheet PDF文件第6页浏览型号CDC2586PAH的Datasheet PDF文件第7页浏览型号CDC2586PAH的Datasheet PDF文件第8页浏览型号CDC2586PAH的Datasheet PDF文件第9页  
CDC2586
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998
D
D
D
D
D
D
Low Output Skew for Clock-Distribution
and Clock-Generation Applications
Operates at 3.3-V V
CC
Distributes One Clock Input to Twelve
Outputs
Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency
No External RC Network Required
External Feedback (FBIN) Synchronizes the
Outputs to the Clock Input
D
D
D
D
D
D
Application for Synchronous DRAM,
High-Speed Microprocessor
TTL-Compatible Inputs and Outputs
Outputs Have Internal 26-Ω Series
Resistors to Dampen Transmission-Line
Effects
State-of-the-Art
EPIC-
ΙΙ
B
BiCMOS Design
Significantly Reduces Power Dissipation
Distributed V
CC
and Ground Pins Reduce
Switching Noise
Packaged in 52-Pin Thin Quad Flat Package
PAH PACKAGE
(TOP VIEW)
GND
1Y1
V
CC
GND
1Y2
V
CC
GND
1Y3
V
CC
GND
GND
2Y1
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
GND
SEL1
SEL0
AGND
FBIN
AGND
AV
CC
CLKIN
NC
AV
CC
OE
TEST
CLR
V
CC
4Y3
GND
V
CC
4Y2
GND
V
CC
4Y1
GND
GND
V
CC
3Y3
GND
GND
2Y2
V
CC
GND
2Y3
V
CC
GND
GND
3Y1
V
CC
NC – No internal connection
description
The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to
precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is
specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or
down to 25 MHz on outputs configured for half-frequency operation. Each output has an internal 26-Ω series
resistor that improves the signal integrity at the load. The CDC2586 operates at nominal 3.3-V V
CC
.
The feedback input (FBIN) synchronizes the output clocks in frequency and phase to CLKIN. One of the twelve
output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs.
The output used as feedback is synchronized to the same frequency as CLKIN.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
GND
3Y2
V
CC
Copyright
©
1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1