CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
D
D
D
D
D
D
Replaces SN74AS304
Maximum Output Skew of 1 ns
Maximum Pulse Skew of 1.5 ns
TTL-Compatible Inputs and Outputs
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
D OR N PACKAGE
(TOP VIEW)
Q3
Q4
GND
GND
GND
Q5
Q6
Q7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q2
Q1
CLR
V
CC
V
CC
CLK
PRE
Q8
description
The CDC304 contains eight flip-flops designed to have low skew between outputs. The eight outputs (in-phase
with CLK) toggle on successive CLK pulses. Preset (PRE) and clear (CLR) inputs are provided to set the Q
outputs high or low independent of the clock (CLK) input.
The CDC304 has output and pulse-skew parameters t
sk(o)
and t
sk(p)
to ensure performance as a clock driver
when a divide-by-two function is required.
The CDC304 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLR
L
H
L
H
H
PRE
H
L
L
H
H
CLK
X
X
X
↑
L
OUTPUTS
Q1– Q8
L
H
L†
Q0
Q0
† This configuration does not persist
when PRE or CLR returns to its
inactive (high) level.
logic symbol
‡
15
16
PRE
CLK
10
11
S
T
1
2
6
7
CLR
14
R
8
9
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1995, Texas Instruments Incorporated
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