CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
D
D
D
D
D
D
Replaces SN74AS305
Maximum Output Skew of 1 ns
Maximum Pulse Skew of 1 ns
TTL-Compatible Inputs and Outputs
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
D OR N PACKAGE
(TOP VIEW)
Q3
Q4
GND
GND
GND
Q5
Q6
Q7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q2
Q1
CLR
V
CC
V
CC
CLK
PRE
Q8
description
The CDC305 contains eight flip-flops designed to have low skew between outputs. The eight outputs (four
in-phase with CLK and four out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC305 has output and pulse-skew parameters t
sk(o)
and t
sk(p)
to ensure performance as a clock driver
when a divide-by-two function is required.
The CDC305 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLR
L
H
L
H
H
PRE
H
L
L
H
H
CLK
X
X
X
L
↑
OUTPUTS
Q1– Q4
L
H
L†
Q0
Q0
Q5– Q8
H
L
L†
Q0
Q0
† This configuration does not persist when
PRE or CLR returns to its inactive (high)
level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1995, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
TI [ TEXAS INSTRUMENTS ]
